Modeling and Transformation of UVM-Compliant Test Benches in MODEVES

MODEVES framework allows the modeling and transformation abilities to perform both formal as well as dynamic ABV through timed automata and SystemVerilog respectively. In the context of dynamic ABV, the test benches required for the simulation of RTL and assertions code need to be implemented separately at lower abstraction level. This creates design and verification gap. To fill this gap in MODEVES framework, the Modeling and Transformation of UVM-Compliant Test Benches is incorporated. The architecture of UVM is shown in Figure below:

Based on UVM low level concepts, meta-model is proposed as shown in Figure below:

Based on proposed meta-model, the modeling of test benches is included in MMM. Furthermore, MODEVES transformation engine is upgraded to generate UVM test benches as well along with SystemVerilog RTL and assertions code. The components are under testing phase and publically available soon as a part of MMM and MTE.