MOdel-based DEsign & Verification for Embedded Systems


This project is divided into several phases. In first phase, UML Profile for SystemVerilog is developed for dynamic Assertion Based Verification. In second phases, a complete end-to end MODEVES framework is developed for both static and dynamic ABV through timed automata and SystemVerilog respectively. The progress is as follows:

Completed Phases :

1. SVOCL SystemVerilog in Object Constraint Language
2. UMLSV - UML Profile for SystemVerilog
3. NLCTL Natural Language for Computation Tree Logic
4. MODEVES Framework as a Whole with both static and dynamic ABV

Ongoing Phases :

1. Modeling and Transformation for UVM Test Benches
2. Support for Portable Test and Stimulus Standard (PSS)
3. Natural Language Processing Framework for Embedded Systems